Table of Contents

Contents:

• Zebra2
• Block functional documentation
  • BITS - Soft inputs and constant bits
  • CLOCKS - Configurable clocks
  • PULSE - One-shot pulse delay and stretch [x4]
  • DIV - Pulse divider [x4]
  • SRGATE - Set Reset Gate
  • LUT - 5 Input lookup table [x8]
  • SEQ - Sequencer
  • COUNTER [x8]
  • PCOMP - Position Compare [x4]
  • PCAP - Position Capture
  • PGEN - Position Generator [x2]
  • INENC - Input encoder
  • LVDSIN - LVDS Input
  • LVDSOUT - LVDS Output
  • OUTENC - Output encoder
  • POSENC - Quadrature and step/direction encoder
  • QDEC - Quadrature Decoder
  • TTLIN - TTL Input
  • FILTER - Filter
  • TTLOUT - TTL Output
• Triggering schemes
  • Fixed exposure gate and trigger
• Unit testing FPGA blocks
  • Python block simulation
  • Unit test sequences
  • Running the test
  • The generated FPGA test vectors
  • Running the FPGA test vectors
  • Generating the plots for the block level documentation
• API doc for configparser